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Every circuit we have seen so far is stateless. Feed in inputs, get outputs. Change the inputs, the outputs change instantly. There is no concept of “what happened before.” But a computer needs to remember things - the value it just computed, which instruction it is executing, whether a loop has finished. This requires a different kind of circuit: one whose output depends not just on current inputs but on past history. These are sequential circuits.

The key ingredient is feedback - routing a gate’s output back as one of its own inputs. This is what makes memory possible.

What state means in hardware. A gate with no feedback just computes: given inputs, it produces an output. Disconnect the inputs, the output is undefined. A circuit with state is different - it holds a value that persists on its own without any external signal actively maintaining it. State is the information the circuit carries from one moment to the next: which instruction is being executed, whether a loop counter has reached zero, what the last computed result was.

How feedback creates stability. Suppose a gate’s output is 1, and that 1 is connected back as one of its inputs. The output reinforces its own cause. Even if the original signal that drove it to 1 disappears, the feedback holds it there. This is a stable state. An external signal can force it to 0, at which point the feedback now reinforces 0 instead. Two stable states, switchable by external signals: that is the complete recipe for a one-bit memory element. The SR latch below is the simplest circuit that implements this recipe, using two NAND gates whose outputs each feed back into the other’s input.

The SR Latch: Memory from Cross-Coupled Gates

Take two NAND gates and connect each one’s output to the other’s input. The circuit has two inputs (Set and Reset, usually written $\overline{S}$ and $\overline{R}$ because they are active-low) and two outputs ($Q$ and $\overline{Q}$).

NAND NAND S̄ R̄ Q Q̄

What happens? Suppose $Q = 1$. That feeds back into the bottom NAND. As long as $\overline{R} = 1$ (not resetting), the bottom NAND outputs 0, which feeds back as the second input to the top NAND, keeping $Q = 1$. The circuit is stable - it stays in this state indefinitely.

Apply $\overline{S} = 0$ (pulse Set): the top NAND is forced to output 1… wait, that would be $Q = 1$. Actually: $\overline{S} = 0$ forces top NAND output to 1 regardless of the other input. That 1 feeds the bottom NAND, which (with $\overline{R} = 1$) outputs 0, which feeds back, reinforcing $Q = 1$ through the cross-coupling. Releasing Set ($\overline{S} = 1$) - the state remains $Q = 1$ because the feedback holds it.

Apply $\overline{R} = 0$ (Reset): the bottom NAND is forced to 1, making $Q = 0$. Release Reset - stays at 0.

The SR latch remembers whether it was last set or reset. This is the simplest memory element.

The forbidden state. Asserting both $\overline{S} = 0$ and $\overline{R} = 0$ simultaneously forces both $Q$ and $\overline{Q}$ to 1, which violates their complementary relationship and causes unpredictable behavior when you release them. This input combination is disallowed.

The D Latch: Clean Data Storage

The SR latch is awkward to use - you need separate Set and Reset signals. The D latch (Data latch) simplifies this: one data input $D$ and one enable input $E$.

When $E = 1$ (enabled), $Q$ follows $D$ - whatever $D$ is, $Q$ becomes it.

When $E = 0$ (disabled), $Q$ holds its last value regardless of what $D$ does.

D E Q E=1: transparent E=0: holds 0 1 0 0 1 (held)

The D latch is built from the SR latch by driving $S$ from $D$ and $R$ from $\overline{D}$ (through a NOT gate), gated through the enable signal. The “forbidden” state can never occur because $S$ and $R$ are always opposite.

Problem with latches: while $E = 1$, the output continuously tracks the input. If the output feeds somewhere that eventually feeds back to the input, changes can ripple around the circuit unpredictably within a single enable cycle. What we really want is to capture the value at a specific instant - a single point in time - not over an interval.

The D Flip-Flop: Edge-Triggered Storage

The D flip-flop solves this by triggering on the edge of the clock signal rather than a level. A rising-edge D flip-flop captures the value of $D$ at the moment the clock transitions from 0 to 1, and holds it until the next rising edge.

D flip-flop D CLK Q Q̄ CLK: ← Q captures D at each ↑ edge

The implementation typically uses a “master-slave” pair of latches: a master latch transparent on the low phase, a slave latch transparent on the high phase. Only the value at the exact low-to-high transition passes through.

Why this matters: all computation in a synchronous digital circuit happens between clock edges. Signals have the entire clock period to propagate and settle. At the next rising edge, all flip-flops simultaneously capture whatever their inputs have settled to, providing a clean “snapshot” of the circuit state.

The Clock

The clock is a signal that oscillates between 0 and 1 at a fixed frequency - the heartbeat of a synchronous digital system.

CLK ↑ capture ↑ capture ↑ capture

The clock rate determines how fast the processor runs. A 3 GHz processor has a clock period of $1/3 \times 10^9 \approx 0.33$ nanoseconds. Every flip-flop in the CPU captures its input on each of those 3 billion rising edges per second.

The maximum clock speed is determined by the critical path - the longest chain of logic gates any signal must traverse between two flip-flops. If that path takes 0.3 ns to settle, the clock period must be at least 0.3 ns, giving a ceiling of about 3.3 GHz.

This is why faster CPUs require either shorter critical paths (simpler or fewer gate stages between registers) or more sophisticated techniques like pipelining that break long paths into shorter segments with intermediate flip-flops.

Registers

A register is simply a bank of D flip-flops sharing a common clock. An 8-bit register holds 8 flip-flops; a 64-bit register holds 64. All 64 bits are captured simultaneously on the rising clock edge.

FF bit 3 FF bit 2 FF bit 1 FF bit 0 CLK 4-bit register: 4 flip-flops, one shared clock

CPU registers - the variables closest to the processor, accessible in a single clock cycle - are exactly this: small banks of flip-flops sitting right on the CPU die. A modern CPU has a few dozen 64-bit registers visible to software, plus hundreds of hidden ones used for pipelining.

Putting It Together: The Feedback Loop

Sequential circuits work by feeding outputs of registers back through combinational logic and into register inputs.

Registers (current state) combinational logic Registers (next state) CLK on next clock edge, next state becomes current state

At each clock edge, the “next state” registers become the “current state.” The combinational logic in between determines the next state from the current one and any external inputs. This pattern - register, combinational logic, register - is the backbone of every CPU, every state machine, every counter, every piece of digital hardware.

Summary

Element Behavior Trigger
SR latch Set/Reset, holds state Level (input level)
D latch Follows input when enabled Level (enable signal)
D flip-flop Captures input snapshot Edge (clock transition)
Register Multi-bit flip-flop bank Edge (shared clock)

Combinational logic computes; sequential logic remembers. Together they form complete computers.

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